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LTC2754 1 2754f typical application features applications description quad 12-/16-bit softspan i out dacs the ltc ? 2754 is a family of quad 12- and 16-bit multiplying serial-input, current-output digital-to-analog converters. they operate from a single 3v to 5v supply and are guar- anteed monotonic over temperature. the LTC2754a-16 provides full 16-bit performance (1lsb inl and dnl, max) over temperature without any adjustments. these softspan? dacs offer six output ranges (up to 10v) that can be programmed through the 3-wire spi serial interface, or pinstrapped for operation in a single range. the content of any on-chip register (including dac out- put-range settings) can be veri? ed in just one instruction cycle; and if you change any register, that register will be automatically read back during the next instruction cycle. voltage-controlled offset and gain adjustments are also provided; and the power-on reset circuit and clr pin both reset the dac outputs to 0v regardless of output range. quad 16-bit v out dac with software-selectable ranges n program or pin-strap six output ranges 0v to 5v, 0v to 10v, C2.5v to 7.5v, 2.5v, 5v, 10v n maximum 16-bit inl error: 1 lsb over temperature n guaranteed monotonic over temperature n low glitch impulse 0.26nv?s (3v), 1.25nv?s (5v) n serial readback of all on-chip registers n low 1a maximum supply current n 2.7v to 5.5v single-supply operation n 16-bit settling time: 2s n voltage-controlled offset and gain trims n clear and power-on-reset to 0v regardless of output range n 52-pin 7mm 8mm qfn package high resolution offset and gain adjustment process control and industrial automation automatic test equipment data acquisition systems LTC2754-16 C + + C dac d dac a v refa v dd v outa v outd r ina refa v refd refd r ofsa gnd m-span r ofsd r comd ge adjd r coma r ind v osadja v osadjd i out2a i out1a i out1d i out2d r fba r fbd ge adja C + spi with readback + C C + + C dac c dac b v refb v outb v outc r inb refb v refc refc r ofsb r ofsc r comc ge adjc r comb r inc v osadjb v osadjc all amplifiers 1/2 lt1469 i out2b i out1b i out1c i out2c r fbb r fbc ge adjb C + + C 2754 ta01 l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. softspan is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents, including 5481178. code 0 C1.0 inl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 16384 32768 2754 g01 C0.6 0.6 0.8 0.2 49152 65535 v dd = 5v v ref = 5v 10v range LTC2754-16 integral nonlinearity (inl)
LTC2754 2 2754f 16 15 17 18 19 top view 53 ukg package 52-lead (7mm s 8mm) plastic qfn 20 21 22 23 24 25 26 51 52 50 49 48 47 46 45 44 43 42 41 33 34 35 36 37 38 39 40 8 7 6 5 4 3 2 1ge adja r ina i out2a gnd cs/ld sdi sck sro srognd v dd gnd i out2d r ind ge adjd ge adjb r inb i out2b gnd ldac s2 s1 s0 m-span rflag clr i out2c r inc ge adjc r coma refa r ofsa r fba i out1a v osadja v osadjb i out1b r fbb r ofsb refb r comb r comd refd r ofsd r fbd i out1d v osadjd v osadjc i out1c r fbc r ofsc refc r comc 32 31 30 29 28 27 9 10 11 12 13 14 t jmax = 150c, ja = 29c/w exposed pad (pin 53) is gnd, must be soldered to pcb absolute maximum ratings i out1x , i out2x to gnd ............................................0.3v r inx , r comx , refx, r fbx , r ofsx , v osadjx , ge adjx to gnd ........................................................18v v dd to gnd .................................................. ?0.3v to 7v digital inputs and outputs to gnd ................ ?0.3v to v dd +0.3v (max 7v) operating temperature range LTC2754c ................................................ 0c to 70c LTC2754i..............................................?40c to 85c maximum junction temperature........................... 150c storage temperature range ...................?65c to 150c (notes 1, 2) pin configuration order information lead free finish tape and reel part marking* package description temperature range LTC2754cukg-12#pbf LTC2754cukg-12#trpbf LTC2754ukg-12 52-lead (7mm 8mm) plastic qfn 0c to 70c LTC2754iukg-12#pbf LTC2754iukg-12#trpbf LTC2754ukg-12 52-lead (7mm 8mm) plastic qfn ?40c to 85c LTC2754bcukg-16#pbf LTC2754bcukg-16#trpbf LTC2754ukg-16 52-lead (7mm 8mm) plastic qfn 0c to 70c LTC2754biukg-16#pbf LTC2754biukg-16#trpbf LTC2754ukg-16 52-lead (7mm 8mm) plastic qfn ?40c to 85c LTC2754acukg-16#pbf LTC2754acukg-16#trpbf LTC2754ukg-16 52-lead (7mm 8mm) plastic qfn 0c to 70c LTC2754aiukg-16#pbf LTC2754aiukg-16#trpbf LTC2754ukg-16 52-lead (7mm 8mm) plastic qfn ?40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel speci? cations, go to: http://www.linear.com/tapeandreel/
LTC2754 3 2754f electrical characteristics v dd = 5v, v ref = 5v unless otherwise speci? ed. the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. symbol param eter conditions LTC2754-12 LTC2754b-16 LTC2754a-16 units min typ max min typ max min typ max static performance resolution 12 16 16 bits monotonicity 12 16 16 bits dnl differential nonlinearity 1 1 0.2 1 lsb inl integral nonlinearity 1 2 0.4 1 lsb ge gain error all output ranges 0.5 2 20 2 12 lsb gain error temp- erature coef? cient gain/temp 1 1 1 ppm/c bze bipolar zero error all bipolar ranges 0.2 1 12 1 8 lsb bipolar zero temp- erature coef? cient 0.5 0.5 0.5 ppm/c psr power supply rejection v dd = 5v, 10% v dd = 3v, 10% 0.025 0.06 0.4 1 0.03 0.1 0.2 0.5 lsb/v lsb/v i lkg i out1 leakage current t a = 25c t min to t max 0.05 2 5 0.05 2 5 0.05 2 5 na na symbol parameter conditions min typ max units analog pins reference inverting resistors (note 4) 16 20 k r ref dac input resistance 810 k r fb feedback resistors (note 3) 810 k r ofs bipolar offset resistors (note 3) 16 20 k r vosadj offset adjust resistors 1024 1280 k r geadj gain adjust resistors 2048 2560 k c iout1 output capacitance full-scale zero-scale 75 45 pf dynamic performance output settling time 0v to 10v range, 10v step. to 0.0015% fs (note 5) 2s glitch impulse v dd = 5v (note 6) v dd = 3v (note 6) 1.25 0.26 nv?s nv?s digital-to-analog glitch impulse (note 7) 2 nv?s reference multiplying bw 0v to 5v range, v ref = 3v rms , code = full scale, C3db bw 2 mhz multiplying feedthrough error 0v to 5v range, v ref = 10v, 10khz sine wave 0.5 mv analog crosstalk (note 8) C109 db thd total harmonic distortion (note 9) multiplying C110 db output noise voltage density (note 10) at i out1 13 nv/ hz v dd = 5v, v ref = 5v unless otherwise speci? ed. the denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c.
LTC2754 4 2754f symbol parameter conditions min typ max units power supply v dd supply voltage 2.7 5.5 v i dd supply current, v dd digital inputs = 0v or v dd 0.5 1 a digital inputs v ih digital input high voltage 3.3v v dd 5.5v 2.7v v dd < 3.3v 2.4 2 v v v il digital input low voltage 4.5v < v dd 5.5v 2.7v v dd 4.5v 0.8 0.6 v v hysteresis voltage 0.1 v i in digital input current v in = gnd to v dd 1 a c in digital input capacitance v in = 0v (note 11) 6pf digital outputs v oh i oh = 200a 2.7v v dd 5.5v v dd C 0.4 v v ol i ol = 200a 2.7v v dd 5.5v 0.4 v timing characteristics the denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. symbol parameter conditions min typ max units v dd = 4.5v to 5.5v t 1 sdi valid to sck set-up 7ns t 2 sdi valid to sck hold 7ns t 3 sck high time 11 ns t 4 sck low time 11 ns t 5 cs /ld pulse width 9ns t 6 lsb sck high to cs /ld high 4ns t 7 cs /ld low to sck positive edge 4ns t 8 cs /ld high to sck positive edge 4ns t 9 sro propagation delay c load = 10pf 18 ns t 10 clr pulse width low 36 ns t 11 ldac pulse width low 15 ns t 12 clr low to rflag low c load = 10pf (note 11) 50 ns t 13 cs /ld high to rflag high c load = 10pf (note 11) 40 ns sck frequency 50% duty cycle (note 12) 40 mhz v dd = 2.7v to 3.3v t 1 sdi valid to sck set-up 9ns t 2 sdi valid to sck hold (note 11) 9ns t 3 sck high time c l = 10pf 15 ns t 4 sck low time 15 ns t 5 cs /ld pulse width 12 ns t 6 lsb sck high to cs /ld high 5ns electrical characteristics v dd = 5v, v ref = 5v unless otherwise speci? ed. the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c.
LTC2754 5 2754f symbol parameter conditions min typ max units t 7 cs /ld low to sck positive edge 5ns t 8 cs /ld high to sck positive edge 5ns t 9 sro propagation delay c load = 10pf 26 ns t 10 clr pulse width low 60 ns t 11 ldac pulse width low 20 ns t 12 clr low to rflag low c load = 10pf (note 11) 70 ns t 13 cs /ld high to rflag high c load = 10pf (note 11) 60 ns sck frequency 50% duty cycle (note 12) 25 mhz timing characteristics the denotes speci? cations that apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: continuous operation above the speci? ed maximum operating junction temperature may impair device reliability. note 3 : because of the proprietary softspan switching architecture, the measured resistance looking into each of the speci? ed pins is constant for all output ranges if the i out1x and i out2x pins are held at ground. note 4: input resistors measured from r inx to r comx ; feedback resistors measured from r comx to refx. note 5: using lt1469 with c feedback = 15pf. a 0.0015% settling time of 1.7s can be achieved by optimizing the time constant on an individual basis. see application note 74, component and measurement advances ensure 16-bit dac settling time. note 6: measured at the major carry transition, 0v to 5v range. output ampli? er: lt1469; c fb = 27pf. note 7. full-scale transition; ref = 0v. note 8. analog crosstalk is de? ned as the ac voltage ratio v outb /v refa , expressed in db. refb is grounded, and dac b is set to 0v-5v span and zero-, mid- or full- scale code. v refa is a 3v rms , 1khz sine wave. crosstalk between other dac channels is similar or better. note 9. ref = 6v rms at 1khz. 0v to 5v range. dac code = fs. output ampli? er = lt1469. note 10. calculation from v n = 4ktrb , where k = 1.38e-23 j/k (boltzmann constant), r = resistance (), t = temperature (k), and b = bandwidth (hz). 0v to 5v range; zero-, mid-, or full- scale. note 11. guaranteed by design, not subject to test. note 12. when using sro, maximum sck frequency f max is limited by sro propagation delay t 9 as follows: f max = 1 2t 9 + t s () ? ? ? ? ? ? ? ? , where t s is the setup time of the receiving device. typical performance characteristics t a = 25c, unless otherwise noted. LTC2754-16 temperature (c) C40 C1.0 inl (lsb) C0.8 C0.4 C0.2 0.0 1.0 0.4 C20 20 0 40 C0.6 0.6 0.8 0.2 60 80 2754 g03 v dd = 5v v ref = 5v 10v range +inl Cinl inl vs temperature integral nonlinearity (inl) differential nonlinearity (dnl) code 0 C1.0 inl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 16384 32768 2754 g01 C0.6 0.6 0.8 0.2 49152 65535 v dd = 5v v ref = 5v 10v range code 0 C1.0 dnl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 16384 32768 2754 g02 C0.6 0.6 0.8 0.2 49152 65535 v dd = 5v v ref = 5v 10v range
LTC2754 6 2754f v ref (v) C10 C8 0 4 4 C6 2 2 6 8 10 2754 g08 v dd = 5v 5v range C1.0 inl (lsb) C0.8 C0.4 C0.2 0.0 1.0 0.4 C0.6 0.6 0.8 0.2 +dnl Cdnl +dnl Cdnl temperature (c) C40 C1.0 dnl (lsb) C0.8 C0.4 C0.2 0.0 1.0 0.4 C20 20 0 40 C0.6 0.6 0.8 0.2 60 80 2754 g04 v dd = 5v v ref = 5v 10v range +dnl Cdnl v ref (v) C10 C8 0 4 4 C6 2 2 6 8 10 2754 g07 v dd = 5v 5v range C1.0 inl (lsb) C0.8 C0.4 C0.2 0.0 1.0 0.4 C0.6 0.6 0.8 0.2 +inl Cinl +inl Cinl dnl vs temperature bipolar zero vs temperature gain error vs temperature inl vs v ref dnl vs v ref typical performance characteristics t a = 25c, unless otherwise noted. LTC2754-16 v dd (v) 2.5 C1.0 inl (lsb) C0.8 C0.4 C0.2 0.0 1.0 0.4 3 4 3.5 4.5 C0.6 0.6 0.8 0.2 5 5.5 2754 g09 +inl Cinl inl vs v dd multiplying frequency response vs digital code frequency (hz) 100 C120 attenuation (db) C100 C80 C60 C40 C20 0 1k 10k 100k 1m 2754 g10 10m all bits off d8 d4 d2 d0 d7 d1 d3 d9 d6 d5 d15 d14 d12 d10 d13 d11 all bits on unipolar 5v output range lt1469 output amplifier c feedback = 8.2pf temperature (c) C40 bze (lsb) C2 0 2 20 60 2754 g05 C4 C6 C8 C20 0 40 4 6 8 80 v dd = 5v v ref = 5v 10v range 0.5ppm/c (typ) temperature (c) C40 ge (lsb) C4 0 4 20 60 2754 g06 C8 C12 C16 C20 0 40 8 12 16 80 v dd = 5v v ref = 5v 10v range 1ppm/c (typ)
LTC2754 7 2754f typical performance characteristics integral nonlinearity (inl) differential nonlinearity (dnl) LTC2754-12 t a = 25c, unless otherwise noted. v dd (v) 2.5 0.5 logic threshold (v) 0.75 1 1.25 1.5 2 3 3.5 4 4.5 5 5.5 1.75 2754 g14 rising falling logic threshold vs supply voltage supply current vs logic input voltage LTC2754 supply current vs clock frequency midscale glitch settling 0v to 10v code 0 C1.0 inl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 1024 2048 2754 g11 C0.6 0.6 0.8 0.2 3072 4095 v dd = 5v v ref = 5v 10v range code 0 C1.0 dnl (lsb) C0.8 C0.4 C0.2 0 1.0 0.4 1024 2048 2754 g12 C0.6 0.6 0.8 0.2 3072 4095 v dd = 5v v ref = 5v 10v range digital input voltage (v) 0 supply current (ma) 3 4 5 4 2754 g13 2 1 0 1 2 3 5 v dd = 5v clr , ldac , sdi, sck, cs/ ld tied together v dd = 3v sck frequency (hz) 1 0.0001 supply current (ma) 0.001 0.01 0.1 1 10 100 v dd = 5v 100 10k 1m 100m 2754 g15 v dd = 3v midscale glitch cs /ld 2v/div v out 5mv/div 500ns/div v dd = 3v v ref = 5v 5v range lt1468 output amplifier c feedback = 27pf 2754 g16 0.26nv?s typ cs /ld 5v/div v out 5mv/div 500ns/div v dd = 5v v ref = 5v 5v range lt1468 output amplifier c feedback = 27pf 2754 g17 1.25nv?s typ 500ns/div cs /ld 5v/div gated settling waveform 250v/div 2754 g17 using lt1469 amp c feedback = 12pf 0v to 10v step rising major carry transition. falling transition is similar or better rising major carry transition. falling transition is similar or better
LTC2754 8 2754f pin functions ge adja (pin1): gain adjust pin for dac a. this control pin can be used to null gain error or to compensate for reference errors. nominal adjustment range is 512 lsb (LTC2754-16) for a voltage input range of v rina (i.e., 5v for a 5v reference input). tie to ground if not used. r ina (pin 2): input resistor for reference inverting ampli? er. the 20k input resistor is connected internally from r ina to r coma . for normal operation tie r ina to the external reference voltage v refa (see typical applications). any or all of these precision-matched resistor sets (each set comprising r inx , r comx and refx) may be used to invert one or more positive reference voltages to the nega- tive voltages needed by the dacs. typically 5v; accepts up to 15v. i out2a (pin 3): dac a current output complement. tie i out2a to ground. gnd (pin 4): ground; provides shielding for i out2a . tie to ground. cs /ld (pin 5): synchronous chip select and load pin. sdi (pin 6): serial data input. data is clocked in on the rising edge of the serial clock (sck) when cs /ld is low. sck (pin 7): serial clock. sro (pin 8): serial readback output. data is clocked out on the falling edge of sck. readback data begins clocking out after the last address bit a0 is clocked in. sro is an active output only when the chip is selected (i.e., when cs /ld is low). otherwise sro presents a high-impedance output in order to allow other parts to control the bus. srognd (pin 9): ground pin for sro. tie to ground. v dd (pin 10): positive supply input; 2.7v v dd 5.5v. by- pass with a 0.1f low-esr ceramic capacitor to ground. gnd (pin 11): ground. tie to ground. i out2d (pin 12): dac d current output complement. tie i out2d to ground. r ind (pin 13): input resistor for reference inverting ampli? er. the 20k input resistor is connected inter- nally from r ind to r comd . for normal operation tie r ind to the external reference voltage v refd (see typical applications). any or all of these precision-matched resis- tor sets (each set comprising r inx , r comx and refx) may be used to invert one or more positive reference voltages to the negative voltages needed by the dacs. typically 5v; accepts up to 15v. ge adjd (pin 14): gain adjust pin for dac d. this control pin can be used to null gain error or to compensate for reference errors. nominal adjustment range is 512 lsb (LTC2754-16) for a voltage input range of v rind (i.e., 5v for a 5v reference input). tie to ground if not used. r comd (pin 15): center tap point for reference ampli? er inverting resistors. the 20k reference inverting resistors are connected internally from r ind to r comd and from r comd to refd, respectively (see block diagram). for normal operation tie r comd to the negative input of external reference inverting ampli? er (see typical applications). refd (pin 16): inverted reference voltage for dac d, with internal connection to the reference inverting resistor. the 20k resistor is connected internally from refd to r comd . for normal operation tie this pin to the output of reference inverting ampli? er (see typical applications). typically C5v; accepts up to 15v. the impedance looking into this pin is 10k to ground (r ind and r comd ? oating). r ofsd (pin 17): bipolar offset network for dac d. this pin provides the translation of the output voltage range for bipolar spans. accepts up to 15v; for normal operation tie to the positive reference voltage at r ind (pin 13). the impedance looking into this pin is 20k to ground. r fbd (pin 18): dac d feedback resistor. for normal operation tie to the output of the i/v converter ampli? er for dac d (see typical applications). the dac output current from i out1d ? ows through the feedback resistor to the r fbd pin. the impedance looking into this pin is 10k to ground. i out1d (pin 19): dac d current output. this pin is a virtual ground when the dac is operating and should reside at 0v. for normal operation tie to the negative input of the i/v converter ampli? er for dac d (see typi- cal applications).
LTC2754 9 2754f pin functions v osadjd (pin 20): dac d offset adjust pin. this control pin can be used to null unipolar offset or bipolar zero error. the offset voltage delta is inverted and attenuated such that a 5v control voltage applied to v osadjd produces v os = -512 lsb (LTC2754-16) in any output range (assumes a 5v reference voltage at r ind ). tie to ground if not used. v osadjc (pin 21): dac c offset adjust pin. this control pin can be used to null unipolar offset or bipolar zero error. the offset voltage delta is inverted and attenuated such that a 5v control voltage applied to v osadjc produces v os = -512 lsb (LTC2754-16) in any output range (assumes a 5v reference voltage at r inc ). tie to ground if not used. i out1c (pin 22): dac c current output. this pin is a virtual ground when the dac is operating and should reside at 0v. for normal operation tie to the negative input of the i/v converter ampli? er for dac c (see typical applications). r fbc (pin 23): dac c feedback resistor. for normal operation tie to the output of the i/v converter ampli? er for dac c (see typical applications). the dac output current from i out1d ? ows through the feedback resistor to the r fbc pin. the impedance looking into this pin is 10k to ground. r ofsc (pin 24): bipolar offset network for dac c. this pin provides the translation of the output voltage range for bipolar spans. accepts up to 15v; for normal operation tie to the positive reference voltage at r inc (pin 28). the impedance looking into this pin is 20k to ground. refc (pin 25): inverted reference voltage for dac c, with internal connection to the reference inverting resistor. the 20k resistor is connected internally from refc to r comc . for normal operation tie this pin to the output of reference inverting ampli? er (see typical applications). typically C5v; accepts up to 15v. the impedance looking into this pin is 10k to ground (r inc and r comc ? oating). r comc (pin 26): center tap point for reference ampli? er inverting resistors. the 20k reference inverting resistors are connected internally from r inc to r comc and from r comc to refc, respectively (see block diagram). for normal operation tie r comc to the negative input of external reference inverting ampli? er (see typical applications). ge adjc (pin 27): gain adjust pin for dac c. this control pin can be used to null gain error or to compensate for reference errors. nominal adjustment range is 512 lsb (LTC2754-16) for a voltage input range of v rinc (i.e., 5v for a 5v reference input). tie to ground if not used. r inc (pin 28): input resistor for reference inverting ampli? er. the 20k input resistor is connected internally from r inc to r comc . for normal operation tie r inc to the external reference voltage v refc (see typical applica- tions). any or all of these precision-matched resistor sets (each set comprising r inx , r comx and r efx ) may be used to invert one or more positive reference voltages to the negative voltages needed by the dacs. typically 5v; accepts up to 15v. i out2c (pin 29): dac c current output complement. tie i out2c to ground. clr (pin 30): asynchronous clear pin. when this pin is low, all dac registers (both code and span) are cleared to zero. all dac outputs are cleared to zero volts. rflag (pin 31): reset flag pin. an active low output is asserted when there is a power-on reset or a clear event. returns high when an update command is executed. m-span (pin 32): manual span control pin. m-span is used in conjunction with pins s2, s1 and s0 (pins 33, 34 and 35) to con? gure all dacs for operation in a single, ? xed output range. to con? gure the part for manual-span use, tie m-span directly to v dd . the active output range is then set via hardware pin strapping of pins s2, s1 and s0 (rather than through the spi port); and write and update commands have no effect on the active output span. to con? gure the part for softspan use, tie m-span di- rectly to gnd. the output ranges are then individually and dynamically controllable through the spi port; and pins s2, s1 and s0 have no effect. see manual span con? guration in the operation sec- tion. m-span must be connected either directly to gnd (softspan con? guration) or to v dd (manual-span con? guration).
LTC2754 10 2754f s0 (pin 33): span bit 0. in manual span mode (m-span tied to v dd ), pins s0, s1 and s2 are pin-strapped to select a single ? xed output range for all dacs. these pins should be tied to either gnd or v dd even if they are unused. s1 (pin 34): span bit 1. in manual span mode (m-span tied to v dd ), pins s0, s1 and s2 are pin-strapped to select a single ? xed output range for all dacs. these pins should be tied to either gnd or v dd even if they are unused. s2 (pin 35): span bit 2. in manual span mode (m-span tied to v dd ), pins s0, s1 and s2 are pin-strapped to select a single ? xed output range for all dacs. these pins should be tied to either gnd or v dd even if they are unused. ldac (pin 36): asynchronous dac load input. when ldac is a logic low, all dacs are updated ( cs /ld must be high). gnd (pin 37): ground; provides shielding for i out2b . tie to ground. i out2b (pin 38): dac b current output complement. tie i out2b to ground. r inb (pin 39): input resistor for reference inverting ampli? er. the 20k input resistor is connected internally from r inb to r comb . for normal operation tie r inb to the external reference voltage v refb (see typical applica- tions). any or all of these precision-matched resistor sets (each set comprising r inx , r comx and refx) may be used to invert one or more positive reference voltages to the negative voltages needed by the dacs. typically 5v; accepts up to 15v. ge adjb (pin 40): gain adjust pin for dac b. this control pin can be used to null gain error or to compensate for reference errors. nominal adjustment range is 512 lsb (LTC2754-16) for a voltage input range of v rinb (i.e., 5v for a 5v reference input). tie to ground if not used. r comb (pin 41): center tap point for reference ampli? er inverting resistors. the 20k reference inverting resistors are connected internally from r inb to r comb and from r comb to refb, respectively (see block diagram). for normal operation tie r comb to the negative input of external reference inverting ampli? er (see typical applications). refb (pin 42): inverted reference voltage for dac b, with internal connection to the reference inverting resistor. the 20k resistor is connected internally from refb to r comb . for normal operation tie this pin to the output of reference inverting ampli? er (see typical applications). typically C5v; accepts up to 15v. the impedance looking into this pin is 10k to ground (r inb and r comb ? oating). r ofsb (pin 43): bipolar offset network for dac b. this pin provides the translation of the output voltage range for bipolar spans. accepts up to 15v; for normal operation tie to the positive reference voltage at r inb (pin 39). the impedance looking into this pin is 20k to ground. r fbb (pin 44): dac b feedback resistor. for normal operation tie to the output of the i/v converter ampli? er for dac b (see typical applications). the dac output current from i out1b ? ows through the feedback resistor to the r fbb pin. the impedance looking into this pin is 10k to ground. i out1b (pin 45): dac b current output. this pin is a virtual ground when the dac is operating and should reside at 0v. for normal operation tie to the negative input of the i/v converter ampli? er for dac b (see typical applications). v osadjb (pin 46): dac b offset adjust pin. this control pin can be used to null unipolar offset or bipolar zero error. the offset-voltage delta is inverted and attenuated such that a 5v control voltage applied to v osadjb produces v os = C512 lsb (LTC2754-16) in any output range (assumes a 5v reference voltage at r inb ). tie to ground if not used. v osadja (pin 47): dac a offset adjust pin. this control pin can be used to null unipolar offset or bipolar zero error. the offset-voltage delta is inverted and attenuated such that a 5v control voltage applied to v osadja produces v os = C512 lsb (LTC2754-16) in any output range (assumes a 5v reference voltage at r ina ). tie to ground if not used. i out1a (pin 48): dac a current output. this pin is a virtual ground when the dac is operating and should reside at 0v. for normal operation tie to the negative input of the i/v converter ampli? er for dac a (see typical applications). r fba (pin 49): dac a feedback resistor. for normal operation tie to the output of the i/v converter ampli? er for dac a (see typical applications). the dac output current from i out1a ? ows through the feedback resistor to the r fba pin. the impedance looking into this pin is 10k to ground. pin functions
LTC2754 11 2754f block diagram dac b 16-bit with span select 16 3 data registers span registers input reg 16 3 data registers input reg span registers dac reg dac reg 39 40 41 42 43 44 45 38 46 21 29 22 23 24 r ofsb refb r inb r inc srognd sro sck sdi s0 s1 s2 m-span cs /ld ldac clr rflag ge adjb r comb i out1b i out2b v osadjb v osadjc ge adjc r fbb i out1c r fbc r ofsc r comc refc i out2c dac c 16-bit with span select 25 26 27 28 36 7 6 5 30 31 33 34 35 32 16 3 data registers span registers dac reg dac reg input reg 16 3 data registers input reg span registers dac reg dac reg 2 1 52 51 50 49 48 3 47 20 12 19 18 17 r ofsa refa r ina r ind ge adja r coma i out1a i out2a v osadja v osadjd ge adjd r fba i out1d r fbd r ofsd r comd refd i out2d 16 15 14 13 dac a 16-bit with span select dac d 16-bit with span select power-on reset 9 gnd 4, 11, 37 8 v dd 10 input reg input reg input reg input reg dac reg dac reg dac b 16-bit with span select control and readback logic 2754 bd LTC2754-16 2.56m 2.56m 2.56m 2.56m 20k 20k 20k 20k 20k 20k 20k 20k r ofsa (pin 50): bipolar offset network for dac a. this pin provides the translation of the output voltage range for bipolar spans. accepts up to 15v; for normal operation tie to the positive reference voltage at r ina (pin 2). the impedance looking into this pin is 20k to ground. refa (pin 51): inverted reference voltage for dac a, with internal connection to the reference inverting resistor. the 20k resistor is connected internally from refa to r coma . for normal operation tie this pin to the output of reference inverting ampli? er (see typical applications). typically C5v; accepts up to 15v. the impedance looking into this pin is 10k to ground (r ina and r coma ? oating). r coma (pin 52): center tap point for reference ampli? er inverting resistors. the 20k reference inverting resistors are connected internally from r ina to r coma and from r coma to refa, respectively (see block diagram). for normal operation tie r coma to the negative input of external reference inverting ampli? er (see typical applications). exposed pad (pin 53): ground. the exposed pad must be soldered to the pcb. pin functions
LTC2754 12 2754f timing diagrams output ranges the LTC2754 is a quad, current-output, serial-input preci- sion multiplying dac with selectable output ranges. ranges can either be programmed in software for maximum ? exibilityeach of the four dacs can be programmed to any one of six output rangesor hardwired through pin-strapping. two unipolar ranges are available (0v to 5v and 0v to 10v), and four bipolar ranges (2.5v, 5v, 10v and C2.5v to 7.5v). these ranges are obtained when an external precision 5v reference is used. when a reference voltage of 2v is used, the ranges become: 0v to 2v, 0v to 4v, 1v, 2v, 4v and C1v to 3v. the output ranges are linearly scaled for other reference voltages. manual span con? guration multiple output ranges are not needed in some applica- tions. to con? gure the LTC2754 to operate in a single span without additional operational overhead, tie the m-span pin directly to v dd . the active output range for all four dacs is then set via hardware pin strapping of pins s2, s1 and s0 (rather than through the spi port); and write and update commands have no effect on the active output span. see figure 1 and table 3. tie the m-span pin to ground for normal softspan operation. figure 1. using m-span to con? gure the LTC2754 for single-span operation (10v range shown). LTC2754-16 m-span s2 s1 s0 2754 f01 cs /ld sdi sck v dd v dd dac a 10v 10v 10v 10v dac b dac c dac d C + C + C + C + sdi sro hi-z cs /ld sck lsb 2754 td lsb t 2 t 9 t 8 t 5 t 7 1 2 31 32 t 6 t 1 ldac t 3 t 4 t 11 operation
LTC2754 13 2754f input and dac registers the LTC2754 has 5 internal registers for each dac, a total of 20 registers (see block diagram). each dac channel has two sets of double-buffered registersone set for the code data, and one for the output range of the dacplus one readback register. double buffering provides the ca- pability to simultaneously update the span (output range) and code, which allows smooth voltage transitions when changing output ranges. it also permits the simultaneous updating of multiple dacs. each set of double-buffered registers comprises an input register and a dac register. input register: the write operation shifts data from the sdi pin into a chosen input register. the input registers are holding buffers; write operations do not affect the dac outputs. dac register: the update operation copies the contents of an input register to its associated dac register. the contents of a dac register directly updates the associated dac output voltage or output range. note that updates always include both data and span registers; but the values held in the dac registers will only change if the associated input register values have previously been changed via a write operation. serial interface when the cs /ld pin is taken low, the data on the sdi pin is loaded into the shift register on the rising edge of the clock (sck pin). the minimum (24-bit wide) loading sequence required for the LTC2754 is a 4-bit command word (c3 c2 c1 c0), followed by a 4-bit address word (a3 a2 a1 a0) and 16 data (span or code) bits, msb ? rst. figure 2 shows the sdi input word syntax to use when writing code or span. if a 32-bit input sequence is used, the ? rst eight bits must be zeros, followed by the same sequence as for a 24-bit wide input. figure 3 shows the input and readback sequences for both 24-bit and 32-bit operations. when cs /ld is low, the sro pin (serial readback output) is an active output.the readback data begins after the command (c3-c0) and address (a3-a0) words have been shifted into sdi. sro outputs a logic low until the readback operation data begins. for a 24-bit input sequence, the 16 readback bits are shifted out on the falling edges of clocks 8-23, suitable for shifting into a microprocessor on the rising edges of clocks 9-24. for a 32-bit sequence, the bits are shifted out on clocks 16-31; see figure 3b. when cs /ld is high, the sro pin presents a high impedance (three-state) output. ldac is an asynchronous update pin. when ldac is taken low, all dacs are updated with code and span data (data in the input buffers is copied into the dac buffers). cs /ld must be high during this operation; otherwise ldac is locked out and will have no effect. the use of ldac is functionally identical to the update all dacs serial input command. the codes for the command word (c3-c0) are de? ned in table 1; table 2 de? nes the codes for the address word (a3-a0). readback in addition to the input and dac registers, each dac has one readback register associated with it. when a read command is issued to a dac, the contents of one of its four buffers (input and dac registers for each of span and code) is copied into its readback register and seri- ally shifted out through the sro pin. figure 3 shows the loading and readback sequences. in the data ? eld (d15-d0) of any non-read instruction cycle, sro shifts out the contents of the buffer that was speci? ed in the preceding command. this rolling readback default mode of operation can dramatically reduce the number of instruction cycles needed, since any command can be veri? ed during succeeding commands with no additional overhead. see figure 4. table 1 shows the storage location (readback pointer) of the data which will be output from sro during the next instruction. for read commands, the data is shifted out during the read instruction itself (on the 16 falling sck edges immediately after the last address bit is shifted in on sdi). when checking the span of a dac using sro, the span bits are the last four bits shifted out, corresponding to their sequence and positions when writing a span. see figure 3.
LTC2754 14 2754f operation table 1. command codes code command readback pointerC current input word w 0 readback pointerC next input word w +1 c3 c2 c1 c0 0010 w rite span dac n set by previous command input span register dac n 0011 w rite code dac n set by previous command input code register dac n 0100 u pdate dac n set by previous command dac span register dac n 0101 u pdate all dacs set by previous command dac code register dac a 0110 w rite span dac n update dac n set by previous command dac span register dac n 0111 w rite code dac n update dac n set by previous command dac code register dac n 1000 w rite span dac n update all dacs set by previous command dac span register dac n 1001 w rite code dac n update all dacs set by previous command dac code register dac n 1010 r ead input span register dac n input span register dac n 1011 r ead input code register dac n input code register dac n 1100 r ead dac span register dac n dac span register dac n 1101 r ead dac code register dac n dac code register dac n 1111 no o peration set by previous command dac code register dac n C system clear C dac span register dac a C initial power-up or power interupt C dac span register dac a codes not shown are reservedCdo not use table 2. address codes a3 a2 a1 a0 n 000 dac a 001 dac b 010 dac c 011 dac d 111 all dacs (note 1) codes not shown are reservedCdo not use. = dont care. note 1. if readback is taken using the all dacs address, the LTC2754 defaults to dac a. table 3. span codes s3 s2 s1 s0 span 0 0 0 unipolar 0v to 5v 0 0 1 unipolar 0v to 10v 0 1 0 bipolar C5v to 5v 0 1 1 bipolar C10v to 10v 1 0 0 bipolar C2.5v to 2.5v 1 0 1 bipolar C2.5v to 7.5v codes not shown are reservedCdo not use. = dont care.
LTC2754 15 2754f readback in m-span con? guration if the part is in m-span con? guration and a dac span register is speci? ed for readback, then the data shifted out of sro will re? ect the actual active span. the hardware- con? gured output range is therefore software detectable and available for use in programming. examples 1. using a 24-bit instruction, load dac a with the unipolar range of 0v to 10v, output at zero volts and all other dacs with the bipolar range of 10v, outputs at zero volts. note all dac outputs should change at the same time. a) cs /ld clock sdi = 0010 1111 0000 0000 0000 0011 b) cs /ld input register- range of all dacs set to bipolar 10v. c) cs /ld clock sdi = 0010 0000 0000 0000 0000 0001 d) cs /ld input register- range of dac a set to unipolar 0v to 10v. e) cs /ld clock sdi = 0011 1111 1000 0000 0000 0000 f) cs /ld input register- code of all dacs set to midscale. g) cs /ld clock sdi = 0011 0000 0000 0000 0000 0000 h) cs /ld input register- code of dac a set to zero code. i) cs /ld clock sdi = 0100 1111 xxxx xxxx xxxx xxxx j) cs /ld update all dacs for both code and range. k) alternatively steps i and j could be replaced with ldac . 2. using a 32-bit load sequence, load dac c with bipolar 2.5v and its output at zero volts. use readback to check input register contents before updating the dac output (i.e., before copying input register contents into dac register). a) cs /ld (note that after power-on, the code in input register is zero) clock sdi = 0000 0000 0011 0100 1000 0000 0000 0000 b) cs /ld input register- code of dac c set to midscale setting. c) cs /ld clock sdi = 0000 0000 0010 0100 0000 0000 0000 0100 data out on sro = 1000 0000 0000 0000 veri? es that input register- code dac c is at midscale setting. d) cs /ld input register- range of dac c set to bipolar 2.5v range. e) cs /ld clock sdi = 0000 0000 1010 0100 xxxx xxxx xxxx xxxx data out on sro = 0000 0000 0000 0100 veri? es that input register- range of dac c set to bipolar 2.5v range. cs /ld f) cs /ld clock sdi = 0000 0000 0100 0100 xxxx xxxx xxxx xxxx g) cs /ld update dac c for both code and range h) alternatively steps f and g could be replaced with ldac . operation
LTC2754 16 2754f operation system offset and reference adjustments the LTC2754 has individual offset- and gain- adjust pins (v osadjx and ge adjx , respectively) for each of its four dacs. many systems require compensation for overall system offset. this may be an order of magnitude or more greater than the offset of the LTC2754, which is so low as to be dominated by external output ampli? er errors even when using the most precise op amps. the offset adjust pins v osadjx can be used to null unipolar offset or bipolar zero error. the offset-voltage delta is inverted and attenuated such that a 5v control voltage applied to v osadjx produces v os = C512 lsb (LTC2754-16) in any output range (assumes a 5v refer- ence voltage at r inx ). in voltage terms, the offset delta is attenuated by a factor of 32, 64 or 128, depending on the output range. (these functions hold regardless of reference voltage.) v os = C(1/128)v osadjx [0v to 5v, 2.5v spans] v os = C(1/64)v osadjx [0v to 10v, 5v, C2.5v to 7.5v spans] v os = C(1/32)v osadjx [10v span] the gain error adjust pins ge adjx can be used to null gain error or to compensate for reference errors. nominal adjustment range is 512 lsb (LTC2754-16) for a volt- age input range of v rinx (i.e., 5v for a 5v reference input). the gain-error delta is non-inverting for positive reference voltages. note that these pins compensate the gain by altering the inverted reference voltage v refx . in voltage terms, the v refx delta is inverted and attenuated by a factor of 128. v refx = C(1/128)ge adjx the nominal input range of these pins is 5v; other volt- ages of up to 15v may be used if needed. however, do not use voltages divided down from power supplies; ref- erence-quality, low-noise inputs are required to maintain the performance of which the part is capable. the v osadjx pins have an input impedance of 1.28m. these pins should be driven with a thevenin-equivalent impedance of 10k or less to preserve the settling performance of the LTC2754. they should be shorted to gnd if not used. the ge adjx pins have an input impedance of 2.56m, and are intended for use with ? xed reference voltages only. they should be shorted to gnd if not used. if the reference inverting resistors are not used for that channel, then ge adjx , r comx and r inx should all be shorted to refx. power-on reset and clear when power is ? rst applied to the LTC2754, all dacs power-up in unipolar 5v mode (s3 s2 s1 s0 = 0000). all internal dac registers are reset to 0 and the dac outputs initialize to zero volts. if the part is con? gured for manual span operation, all four dacs will be set into the pin-strapped range at the ? rst update command. this allows the user to simultaneously update span and code for a smooth voltage transition into the chosen output range. when the clr pin is taken low, a system clear results. the dac buffers are reset to 0 and the dac outputs are all reset to zero volts. the input buffers are left intact, so that any subsequent update command (including the use of ldac ) restores the addressed dacs to their respective previous states. if clr is asserted during an instruction, i.e., when cs /ld is low, the instruction is aborted. integrity of the relevant input buffers is not guaranteed under these conditions, therefore the contents should be checked using readback or replaced. the rflag pin is used as a ? ag to notify the system of a loss of data integrity. the rflag output is asserted low at power-up, system clear, or if the supply v dd dips below approximately 2v; and stays asserted until any valid update command is executed.
LTC2754 17 2754f operation c2 c1 c0 a3 a2 a1 a0 d15 msb d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 lsb c3 LTC2754-16 (write code) control word address word 16-bit code sdi c2 c1 c0 a3 a2 a1 a0 d11 msb d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 lsb c3 LTC2754-12 (write code) control word address word 12-bit code 4 zeros c2c1c0a3a2a1a00000 00000000s3s2s1s0 c3 LTC2754-16 LTC2754-12 (write span) control word address word 12 zeros span 2754 f02 figure 2. serial input write sequence
LTC2754 18 2754f 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 0 0 0 0 0 0 0 0 cs /ld sck sdi control word address word dac code or dac span 32-bit data stream 0 0 0 0 0 0 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 sro t 2 t 3 t 4 t 1 t 9 d15 17 sck sdi sro d14 d15 18 d14 8 zeros hi-z hi-z readback code 2754 f04 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 s3 s2 s1 s0 0 0 0 0 0 0 0 0 0 sro readback span span 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 c2 c1 c0 a3 a2 a1 a0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 c3 0 0 0 0 0 0 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 cs /ld sck sdi sro hi-z hi-z control word readback code 0000000000000000000s3s2s1s0 0 sro readback span address word dac code or dac span 24-bit data stream 2754 f03 span figure 3a. 24-bit instruction sequence figure 3b. 32-bit instruction sequence operation
LTC2754 19 2754f operation sdi sro ... write data dac a read input data register dac a write data dac b read input data register dac b write data dac c read input data register dac c write data dac d read input data register dac d update all dacs read dac data register dac a ... 2754 f04 figure 4. rolling readback
LTC2754 20 2754f applications information op amp selection because of the extremely high accuracy of the 16-bit LTC2754-16, careful thought should be given to op amp selection in order to achieve the exceptional performance of which the part is capable. fortunately, the sensitivity of inl and dnl to op amp offset has been greatly reduced compared to previous generations of multiplying dacs. tables 4 and 5 contain equations for evaluating the effects of op amp parameters on the LTC2754s accuracy when programmed in a unipolar or bipolar output range. these are the changes the op amp can cause to the inl, dnl, unipolar offset, unipolar gain error, bipolar zero and bipolar gain error. tables 4 and 5 can also be used to determine the effects of op amp parameters on the LTC2754-12. however, the results obtained from tables 4 and 5 are in 16-bit lsbs. divide these results by 16 to obtain the correct lsb sizing. table 6 contains a partial list of ltc precision op amps recommended for use with the LTC2754. the easy-to-use design equations simplify the selection of op amps to meet table 4. coef? cients for the equations in table 5 output range a1 a2 a3 a4 a5 5v 1.1 2 1 1 10v 2.2 3 0.5 1.5 5v 2 2 1 1 1.5 10v 4 4 0.83 1 2.5 2.5v 1 1 1.4 1 1 C2.5v to 7.5v 1.9 3 0.7 0.5 1.5 a3 ? v os1 ? 19.8 ? i b1 ? 0.13 ?? 0 a4 ? v os2 ? 13.1 ? a4 ? i b2 ? 0.13 ?? a4 ? () 5v v ref () 5v v ref () 16.5k a vol1 op amp v os1 (mv) i b1 (na) a vol1 (v/v) v os2 (mv) i b2 (mv) a vol2 (v/v) v os1 ? 3.2 ? i b1 ? 0.0003 ?? a1 ? 0 0 0 inl (lsb) () 5v v ref () 5v v ref () 1.5k a vol1 () 66k a vol2 () 131k a vol1 () 131k a vol1 () 131k a vol2 () 131k a vol2 v os1 ? 0.82 ? i b1 ? 0.00008 ?? a2 ? 0 0 0 dnl (lsb) () 5v v ref () 5v v ref a3 ? v os1 ? 13.2 ? i b1 ? 0.13 ?? 0 0 0 0 unipolar offset (lsb) () 5v v ref () 5v v ref () 5v v ref v os1 ? 13.2 ? i b1 ? 0.0018 ? a5 ? v os2 ? 26.2 ? i b2 ? 0.26 ? bipolar gain error (lsb) () 5v v ref () 5v v ref () () () 5v v ref () 5v v ref bipolar zero error (lsb) unipolar gain error (lsb) () 5v v ref () 5v v ref () 5v v ref () 5v v ref () 5v v ref v os1 ? 13.2 ? i b1 ? 0.0018 ? a5 ? v os2 ? 26.2 ? i b2 ? 0.26 ? table 5. easy-to-use equations determine op amp effects on dac accuracy in all output ranges (circuit of page 1). subscript 1 refers to output amp, subscript 2 refers to reference inverting amp. table 6. partial list of ltc precision ampli? ers recommended for use with the LTC2754 with relevant speci? cations amplifier amplifier specifications v os v i b na a vol v/mv voltage noise nv/ hz current noise pa/ hz slew rate v/s gain bandwidth product mhz t settling with ltc2755 s power dissipation mw lt1001 25 2 800 10 0.12 0.25 0.8 120 46 lt1097 50 0.35 1000 14 0.008 0.2 0.7 120 11 lt1112 (dual) 60 0.25 1500 14 0.008 0.16 0.75 115 10.5/op amp lt1124 (dual) 70 20 4000 2.7 0.3 4.5 12.5 19 69/op amp lt1468 75 10 5000 5 0.6 22 90 2 117 lt1469 (dual) 125 10 2000 5 0.6 22 90 2 123/op amp
LTC2754 21 2754f applications information the systems speci? ed error budget. select the ampli? er from table 6 and insert the speci? ed op amp parameters in table 5. add up all the errors for each category to de- termine the effect the op amp has on the accuracy of the part. arithmetic summation gives an (unlikely) worst-case effect. a root-sum-square (rms) summation produces a more realistic estimate. op amp offset will contribute mostly to output offset and gain error, and has minimal effect on inl and dnl. for example, for the LTC2754-16 with a 5v reference in 5v unipolar mode, a 250v op amp offset will cause a 3.3lsb zero-scale error and a 3.3lsb gain error; but only 0.8lsb of inl degradation and 0.2lsb of dnl degradation. while not directly addressed by the simple equations in tables 4 and 5, temperature effects can be handled just as easily for unipolar and bipolar applications. first, con- sult an op amps data sheet to ? nd the worst-case v os and i b over temperature. then, plug these numbers into the v os and i b equations from table 5 and calculate the temperature-induced effects. for applications where fast settling time is important, ap- plication note 74, component and measurement advances ensure 16-bit dac settling time, offers a thorough discus- sion of 16-bit dac settling time and op amp selection. precision voltage reference considerations much in the same way selecting an operational ampli? er for use with the LTC2754 is critical to the performance of the system, selecting a precision voltage reference also requires due diligence. the output voltage of the LTC2754 is directly affected by the voltage reference; thus, any voltage reference error will appear as a dac output volt- age error. there are three primary error sources to consider when selecting a precision voltage reference for 16-bit applications: output voltage initial tolerance, output voltage temperature coef? cient and output voltage noise. initial reference output voltage tolerance, if uncorrected, generates a full-scale error term. choosing a reference with low output voltage initial tolerance, like the lt1236 (0.05%), minimizes the gain error caused by the reference; however, a calibration sequence that corrects for system zero- and full-scale error is always recommended. a references output voltage temperature coef? cient af- fects not only the full-scale error, but can also affect the circuits apparent inl and dnl performance. if a refer- ence is chosen with a loose output voltage temperature coef? cient, then the dac output voltage along its transfer characteristic will be very dependent on ambient conditions. minimizing the error due to reference temperature coef- ? cient can be achieved by choosing a precision reference with a low output voltage temperature coef? cient and/or tightly controlling the ambient temperature of the circuit to minimize temperature gradients. table 7. partial list of ltc precision references recommended for use with the LTC2754 with relevant speci? cations reference initial tolerance temperature drift 0.1hz to 10hz noise lt1019a-5, lt1019a-10 0.05% 5ppm/c 12v p-p lt1236a-5, lt1236a-10 0.05% 5ppm/c 3v p-p lt1460a-5, lt1460a-10 0.075% 10ppm/c 20v p-p lt1790a-2.5 0.05% 10ppm/c 12v p-p ltc6652a-2.048 0.05% 5ppm/c 2.1ppm p-p ltc6652a-2.5 2.1ppm p-p ltc6652a-3 2.1ppm p-p ltc6652a-3.3 2.2ppm p-p ltc6652a-4.096 2.3ppm p-p ltc6652a-5 2.8ppm p-p
LTC2754 22 2754f as precision dac applications move to 16-bit and higher performance, reference output voltage noise may contrib- ute a dominant share of the systems noise ? oor. this in turn can degrade system dynamic range and signal-to- noise ratio. care should be exercised in selecting a voltage reference with as low an output noise voltage as practi- cal for the system resolution desired. precision voltage references, like the lt1236, produce low output noise in the 0.1hz to 10hz region, well below the 16-bit lsb level in 5v or 10v full-scale systems. however, as the circuit bandwidths increase, ? ltering the output of the reference may be required to minimize output noise. grounding as with any high resolution converter, clean grounding is important. a low impedance analog ground plane and star grounding techniques should be used. i out2x must be tied to the star ground with as low a resistance as possible. applications information when it is not possible to locate star ground close to i out2 , a low resistance trace should be used to route this pin to star ground. this minimizes the voltage drop from this pin to ground caused by the code-dependent current ? owing to ground. when the resistance of this circuit board trace becomes greater than 1, a force/sense am- pli? er con? guration should be used to drive this pin (see figure 5). this preserves the excellent accuracy (1lsb inl and dnl) of the LTC2754-16. layout figures 6, 7, 8, and 9 show the layout for the LTC2754 evaluation board, dc1546. this shows how to route the digital signals around the device without interfering with the reference and output op amps. complete demo board documentation is available in the dc1546 quick start guide.
LTC2754 23 2754f figure 5. optional circuits for driving i out2 from gnd with a force/sense ampli? er. applications information C + C + 1/2 lt1469 1/2 lt1469 dac a LTC2754-16 v ref 5v 2 1 3 48 49 50 2 1 52 1 51 i out1a 15pf i out2a r fba v osadja refa r coma r ina r ofsa v outa 3 47 C + 6 1 23 i out2 2 3 *schottky barrier diode zetex* bat54s lt1001 2754 f05 1000pf alternate amplifier for optimum settling time performance 6 1 23 3, 12, 29, 38 C + lt1468 3 zetex bat54s 2 200 200 7 i out2 150pf 3 2 dac b dac c dac d C + C + C + ge adja
LTC2754 24 2754f applications information figure 6. LTC2754 evaluation board dc1546. layer 1, top layer (component side) figure 7. LTC2754 evaluation board dc1546. layer 2, gnd plane 2754 f07 2754 f06
LTC2754 25 2754f figure 8. LTC2754 evaluation board dc1546. layer 3, power traces figure 9. LTC2754 evaluation board dc1546. layer 4, bottom layer (solder side) applications information 2754 f08 2754 f09
LTC2754 26 2754f typical application digitally controlled offset and gain trim circuit. powering v dd from lt1236 ensures quiet supply to lt1991 to lt1991 ge adja ge adjb ge adjc ge adjd gnd 1 gnd gnd gnd srognd r ina 2 r fba 49 r ofsa refa 50 51 refb 42 r coma 52 r fbb 44 r ofsb 43 r inc r ind r fbc r ofsd r fbd v osadjd i out2d r comc r comd r ofsc refc refd 40 450k v + v C out 6 7 5 4 lt1991 ref 4f 27 to lt1991s 14 4 11 37 53 28 5v 26 13 15 25 24 23 16 17 18 20 12 27pf lt1469 to lt1991 v + v C i out1d 19 9 + C 150pf 150pf i out2c 29 v osadjc 21 27pf lt1469 1 8 2 3 6 5 4 v outa 2754 ta02 v outc v outb v outd lt1469 v + v C + C 8 7 2 3 4 lt1469 v + v C + C + C 8 2 3 4 4 8 7 2 3 4 8 7 6 5 4 8 7 v + v C i out1c 22 + C i out2b 38 v osadjb 46 27pf v + v C i out1b 45 + C i out2a 3 v osadja 47 27pf v + v C i out1a rflag clr 48 + C 150pf v C v + + C 8 1 2 3 4 v + v C + C 8 7 6 5 4 150pf r rcomb LTC2754 41 r inb 39 v dd sdi cs /ld 5v 10 30 31 5 6 sck 7 sro 2 3 4 5 12 13 14 15 7 8 9 10 6 8 m-span 32 s2 35 s1 34 s0 33 ldac 36 10k lt1236-5 in out trim gnd 4 6 2 v + 5 10f 0.1f t0 additional offset adjust circuits t0 additional gain adjust circuits 0.1f 10k cs 1 sdi sck sdo cs 2 0.1f 10f 10k 10k v outa v outb v outc v outd v oute v outf v outg v outh cs /ld sck sdi clr ldac v cc ref ltc2636 16 gnd 1 11 5v 4f 450k 450k 150k 50k m9 m3 m1 50k 450k 150k p1 p3 p9 8 9 10 1 2 3 450k v + v C out 6 7 5 4 lt1991 ref 4f + C 4f 450k 450k 150k 50k m9 m3 m1 50k 450k 150k p1 p3 p9 8 9 10 1 2 3
LTC2754 27 2754f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. ukg package 52-lead plastic qfn (7mm 8mm) (reference ltc dwg # 05-08-1729 rev ?) 7.00 0.10 (2 sides) note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.30 typ or 0.35 45 c chamfer 0.40 0.10 52 51 1 2 bottom viewexposed pad top view side view 6.50 ref (2 sides) 8.00 0.10 (2 sides) 5.50 ref (2 sides) 0.75 0.05 0.75 0.05 r = 0.115 typ r = 0.10 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 C 0.05 6.45 0.10 5.41 0.10 0.00 C 0.05 (ukg52) qfn rev ? 0306 5.50 ref (2 sides) 5.41 0.05 6.45 0.05 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 6.10 0.05 7.50 0.05 6.50 ref (2 sides) 7.10 0.05 8.50 0.05 0.25 0.05 0.50 bsc package outline package description
LTC2754 28 2754f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0609 ? printed in usa related parts part number description comments lt1027 precision reference 1ppm/c maximum drift lt1236a-5 precision reference 0.05% maximum tolerance, 1ppm 0.1hz to 10hz noise lt1468 16-bit accurate op-amp 90mhz gbw, 22v/s slew rate lt1469 dual 16-bit accurate op-amp 90mhz gbw, 22v/s slew rate ltc1588/ltc1589/ ltc1592 serial 12-/14-/16-bit i out single dac software-selectable (softspan) ranges, 1lsb inl, dnl, 16-lead ssop package ltc1591/ltc1597 parallel 14-/16-bit i out single dac integrated 4-quadrant resistors ltc2704 serial 12-/14-/16-bit v out quad dacs software-selectable (softspan) ranges, integrated ampli? ers, 1lsb inl ltc2751 parallel 12-/14-/16-bit i out softspan single dac 1lsb inl, dnl, software-selectable (softspan) ranges, 5mm 7mm qfn-38 package ltc2753 parallel 12-/14-16-bit i out softspan dual dacs 1lsb inl, dnl, software-selectable (softspan) ranges, 7mm 7mm qfn-48 package ltc2755 parallel 12-/14-/16-bit i out softspan quad dacs 1lsb inl, dnl, software-selectable (softspan) ranges, 9mm 9mm qfn-64 package

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